Embodiments relate in general to the field of developing integrated electrical circuits, and in particular to a method for reducing power consumption of an electronic circuit, and a system for reducing power consumption of an electronic circuit. Still more particularly, embodiments relate to a data processing program and a computer program product for reducing power consumption of an electronic circuit.
In CMOS technology, glitch power dissipated in combinational circuits owns an important portion of the total dynamic power consumption. Conventional methods for power estimation include called Monte Carlo Simulation (MCS). For this technique, a digital simulator and information about gate and interconnect delays are necessary. The runtime of MCS is high.
Statistical Methods (SM), e.g. IMS-PE, CREST, TPS, are also extensively investigated techniques. SMs are like one-period simulation using a special gate model which requires signal probabilities instead of multi-valued logic. It's faster than Monte Carlo simulation. The nature of SM is like a one-period digital simulation. Therefore, its runtime is still not low enough. In the lack of consideration of correlations the accuracy is also limited. Test cases have shown that especially the estimated power on the nets near the POs may show up to 400% error.
In VLSI design, great attention is paid to the power consumption of circuits. Research covers power estimation and power optimization from system to electrical level. The challenge of lower-level power estimation is to find a reasonable trade-off between computational effort and accuracy of power estimation. For instance, the tools based on SMs can estimate the dynamic power of combinational circuits very efficiently. However, they all suffer more or less from a poor accuracy. Especially, if the dynamic power per net is considered, a satisfying accuracy cannot be reached.
In CMOS circuits, power is dissipated due to the static leakage current and the dynamic current caused by signal transition. During the signal transition a dynamic current flows through the transistor and charges or discharges the parasitic capacitances. The appropriate power is called dynamic power. It can be modeled according to equation (1):
                              P          dynamic                =                              ∑            n                    ⁢                                    1              2                        ⁢                          V              dd              2                        ⁢                          C              n                        ⁢                          f              c                        ⁢                          α              n                                                          (        1        )            
Wherein Vdd, fc, Cn, and αn are supply voltage, clock frequency, net capacitance and signal transition rate, respectively. It is obvious that besides scaling down supply voltage and clock frequency, one can also reduce the product of transition rate and net capacitance or either of them to reduce dynamic power.
In combinational circuits, signals are expected to change at most once in one clock period. However, there are almost always unnecessary signal transitions, which are called glitches. If the timing conditions such as setup-time and hold-time of the registers are satisfied, the circuit can still work. However, the signal transition rate an is increased due to the glitches, and therefore more power is consumed by the unnecessary signal transitions. If glitches can be eliminated, dynamic power is reduced. Glitches are caused by different arrival times of signals at the inputs of the gate.
Algorithms were proposed to optimize dynamic power consumption. For full-custom design, power optimization algorithms can result in a glitch-free design. A conventional technique is called path balancing. Besides, hazard filtering is another technique proposed which can be considered as an extension of path balancing. It shows that it is not necessary to balance the signal path exactly to eliminate the glitches. This technique indicates that the gate inertia can stop not only the generation but also the propagation of glitches. According to hazard filtering, a glitch free design needs to satisfy the requirement that the differences of signal arrival times at the inputs of all gates in the circuit must be less than their inertial delays.
Conventional techniques apply a zero-delay model in the simulation to reduce the number of events per period since if normal delay model (non-zero delay model) is applied in the simulation, lots of events could probably be generated in every clock period to model the circuit behavior. In applying the zero-delay model the whole simulation must be shorter, obviously, because the number of events per period is no more than the number of the gates in the circuit. However, the accuracy would be destroyed, if no further method would be employed to take care of the glitches.